CASCON Interconnect Test

Stuck-At Test Phase

Stuck-at-Low Test:

All Boundary Scan nets are maintained at a HIGH logic level by default to decouple this test from short-circuit testing. Every driver-capable pin drives a HIGH level at least once while all receiver and bidirectional pins measure the line.

Stuck-at-High Test:

In an analogous manner, all nets are kept at a LOW logic level by default while each driver pin drives a LOW level at least once and receiver pins capture the value.

Vector Count:

The theoretical number of test steps required for each stuck-at section is determined by the bus net containing the highest number of driver-capable pins.

Test for Shorts (Counter Test Phase)

Net Independence Verification:

This phase checks that all Boundary Scan nets are electrically independent from one another.

Binary Counting Sequence:

The algorithm assigns a unique binary counting sequence (such as ...0001, ...0010, ...0011) across the nets. This guarantees that for every pair of nets, there is at least one test step where they are driven to opposing logic levels.

Vector Count:

The number of generated test vectors for the counter test scales logarithmically as log₂ (number of nets).

Offset & Additional Counter Test:

If hardware constraints prevent full coverage with the basic counting sequence, a counter test offset or an additional counter test is applied to resolve remaining ambiguity.

Fault Diagnosis Execution

Inverse Counter Tests: 

While basic Go/NoGo testing uses only the stuck-at and counter tests, full fault diagnosis generates inverse counter tests (and inverse additional counter tests) where all vector levels are negated.

Pairwise Level Condition:

This ensures that for any given pair of nets, net A drives LOW while net B drives HIGH in at least one step, and vice versa in another step.

Two-Step Diagnostic Evaluation:

1. Stuck-at Faults:

   Nets or input pins that consistently measure a single state regardless of driven values are flagged as stuck-at errors and excluded from short-circuit analysis.

2. Shorts Detection:

   Pins or nets showing identical measured levels across all test steps are identified as shorted together.

Tests for tri-state conditions and pull-up / pull-down resistors are integrated into the initialization and stuck-at test phases:

Test of Pull-Up and Pull-Down Resistors

When nets are assigned PULL_UPor PULL_DOWN attributes in the netlist (*.CNL) or generator settings (*.EGS), the Automatic Test Pattern Generator (ATPG) incorporates pull-resistor verification directly into the Stuck-At Test Phase:

• Pull-Up Resistor Test (Stuck-at-High Section):
  • Integrated into the stuck-at-high test, where background nets default to a LOW level.
  • Step 1: The Boundary Scan driver actively drives the net LOW.
  • Step 2 (Tristate Step): The driver switches to a high-impedance (tristate) state, releasing the line.
  • Step 3: The subsequent  Capture-DR operation checks whether the line recharges to a HIGH level via the pull-up resistor.
• Pull-Down Resistor Test (Stuck-at-Low Section):
  • Integrated into the stuck-at-low test, following the inverse logic.
  • The net is actively driven HIGH, placed into tristate, and then captured to verify that the pull-down resistor pulls the line back to LOW.
• Dynamic Timing Requirement:
  • To distinguish between a true pull resistor and a floating line slowly charging via stray capacitance, the update-to-capture delay is set to "FAST (2.5 TCK)".
  • The TCK clock frequency must be fast enough so that 2.5 TCK cycles elapse before an un-pulled, floating net can naturally drift.

Test of Tri-State Conditions

Tri-state (high-impedance) checks and conditions occur at three distinct points in the interconnect test workflow:

• Initial Preload Vector:

  • Before active test vectors are applied, the ATPG can generate an initial preload step ("Tristate instead Safe Value Step first").

    This initializes all Boundary Scan driver cells to high-impedance, preventing signal contention across the board at test startup.

• Driver Control in Resistor Tests:
  • During the pull-up and pull-down test steps, the algorithm explicitly forces driving pins into high-impedance (Z) to ensure that driver disable control cells are fully functional and that the driver is not holding the line.
• Decoupling Non-Tested or Cluster Nets:

  • For nets or devices that should not actively drive during the interconnect test, pins can be forced into high-impedance using device instructions such as  HIGHZ or  SAMPLE_Z (if available) or with pin-specific disable settings in the *.EGS file.

    Non-cluster Boundary Scan nets can also default to TRISTATE.

For a discussion of IEEE 1149.6 interconnect testing, see this article.