IEEE 1149.6 support in SYSTEM CASCON

In SYSTEM CASCON, IEEE 1149.6 testing is directly integrated into the standard Interconnection Test workflow. While standard IEEE 1149.1 only performs quasi-static DC structural testing (which fails on AC-coupled lines with in-line capacitors), IEEE 1149.6 introduces dynamic pulse signal generation and receivers to test AC-coupled nets and advanced differential I/O networks.

Here is how IEEE 1149.6 testing fits into the interconnect test algorithm and generation process:

1. Automatic Integration & Generation

• Detection: When BSDL files for IEEE 1149.6–compliant devices are included in the UUT description, CASCON automatically detects them and enables the 1149.6 options in the Interconnection Test settings.
• Dedicated Test Section: When enabled, CASCON generates a separate test section specifically for IEEE 1149.6 testing alongside the standard stuck-at and counter tests.
• Capacitance Requirements: Test generation evaluates the capacitance values of couple-capacitors specified for the AC-coupled networks.

2. Special 1149.6 Test Instructions

During the 1149.6 test section, the algorithm replaces the default EXTEST instruction with standard-specific AC instructions:

• EXTEST_PULSE (Default): Selected driver outputs toggle one time while the TAP controller resides in the RunTest/Idle state.
• EXTEST_TRAIN (Optional): Selected driver outputs toggle continuously as a pulse train as long as TCK is applied in RunTest/Idle.

3. Timing and Control Parameters (Enhanced DC Testing)

Because AC signals decay through coupling capacitors, precise TAP controller timing is configured in the Advanced Options:

• T-Test / Extest_PULSE TCK Number: Defines the minimum retention time spent in RunTest/Idle  while EXTEST_PULSE is active. This delay must be long enough so that successive signal edges at the receiver's low-pass filter do not erase each other.
• Extest_TRAIN TCK Number & min. TCK Period: Specifies the number of pulse transitions and the minimum TCK cycle time when EXTEST_TRAIN is utilized.
• Noise Reduction: Option to insert a second SHIFT operation with identical values after each primary SHIFT  operation. This prevents DC switching operations during the second UPDATE, reducing noise and disturbance to the AC switching signals.
• Non-BScan Net Control: Non-1149.6 nets can be explicitly held at static logic levels (Hold Low, Hold High , or Don't Care) during the 1149.6 test execution.

4. Hardware Receiver Support

During execution, compliant boundary-scan ICs and tester hardware (such as CION-LX devices) utilize built-in 1149.6 test receivers. These receivers consist of comparators with programmable hysteresis levels (V_HYST), low-pass filters, and test mode switches that convert high-speed AC edges back into digital logic values for the CaptureDR operation.